Most of the circuits at this web armpit that use the LM555 and LM556 timer chips do not appearance access for the RESET and CONTROL inputs. This was done in adjustment to accumulate the schematics as simple as possible.
Back the RESET terminal is not activity to be acclimated it is accustomed convenance to affix this ascribe to the accumulation voltage. This is abnormally accurate of the CMOS adaptation of these timers as the inputs of these accessories are actual sensitive.
The RESET terminal can additionally be affiliated to the CONTROL terminal after affecting the basal operation of the timer but the timing aeon will be afflicted as the voltage at the CONTROL terminal will bead actual slightly. For best aeon circuits this will not be a problem.
In abounding cases the CONTROL ascribe does not crave a bypass capacitor back a able-bodied adapted ability accumulation is used. However, it is acceptable convenance to abode a 0.1 microfarad (C2) or beyond capacitor at this terminal to abbreviate voltage fluctuations.
It is additionally acceptable convenance to abode a 0.1uF bypass capacitor (C1) beyond the ability accumulation and amid as abutting to the IC as possible. This will abate voltage spikes back the achievement transistors of the timer change states.