LiteSpeed Load Balancer

LiteSpeed Load Balancer (LSLB) is a high-performance, content-aware, session-aware HTTP application load balancer. It can forward requests based on request content as well as session stickiness preference. LiteSpeed Load Balancer can help scale your application beyond one server deployment, as well as improve the reliability of your service in case of hardware failures.

We offer 15-day risk free trials and a 30-day money back guarantee.

Features

HTTP/1.1, HTTP/1.0 backward compatible

Supports HTTP, LiteSpeed SAPI, FastCGI and AJPv13 back ends

Load balance algorithms: round-robin, least load, least session

Session affinity with fail-over

Directing request based on domain names, request URL, Cookie, SSL Session, etc.

Content aware: route request based on request content

Dynamic response compression/decompression (gzip)

Gzip compression with backend HTTP Server

Automatic HTTP protocol upgrade/downgrade to maintain persistent connection with backend servers

Massive shared hosting: load balance to millions of websites

URL rewrite

SSL acceleration

Geotargeting support

IPv6 support

Anti-(D)DoS attacks capability

Request filtering (HTTP firewall), filter attacking requests based on request content

Chroot for enhanced security

Backend server health monitoring

Web administration console

Online upgrade to keep your server up-to-date

Security

LiteSpeed load balancer is designed to be a secure load balancer. With chroot jail, IP level bandwidth throttling, connection accounting, strict HTTP request checking, and URL context filtering, DoS effects are minimized and backend cluster is properly fenced away from the HTTP request layer reducing vulnerability.

High performance Secure HTTP (HTTPS): supports SSLv2, SSLv3 and TLSv1

IP level throttling (Bandwidth and Request Rate)

Comprehensive IP level connection accounting

Hotlink protection

Strict HTTP request checking

External application firewall for dynamic content

Chroot whole server process

Reliability

Zero downtime maintanance (include reconfiguration, software upgrade)

Watch dog and Instant recovery maximizes up-time

Graceful shutdown, all requests in process will be completed.

Runs completely in the user space, OS reliability is not affected

The following section provides a brief overview of the above security features. Access Control: Server, virtual host and directory (context) level access control which can allow or block traffic from specific IP/sub-networks. IP Level Throttling Limits network bandwidth to and from a single IP address regardless of the number of connections. IP Level Connection Accounting Limits the number of concurrent connections from a single IP address. It is controlled by the Connection Soft Limit, Connection Hard Limit, Grace Period, and Banned Period values. Strict Request Checking Every HTTP request is strictly checked by LiteSpeed load balancer:

Request size is limited by the Max Request URL Length, Max Request Header Length, and Max Request Body Length values. Strict Static File Checking LiteSpeed web server will serve a static file only if the following conditions are satisfied:

"/.ht*" and "/.svn*" are not allowed in a decoded URL, this will deny accessing some important hidden files and directories.

the file permission must contain configured required permission bits.

the file permission must not contain any configured restricted permission bits.

The file is not in the Access Denied Directory list

does not contain symbolic links if symbolic linking is not allowed.

LiteSpeed load balancer does not index a directory by listing its files.

LiteSpeed load balancer can pipeline requests and control the concurrency level of external applications to prevent over consumption of system resources. It only forwards completed requests to external applications and caches the response. Thus external applications will be immediately available to process the next request without waiting for the response to be completely received by the client. In this way, the server can utilize fewer instances of external applications to serve more concurrent requests and will achieve higher performance and scalability. LiteSpeed load balancer uses its own virtual memory to cache the request and response body to minimize the usage of system memory without sacrificing performance.

Chroot Jail

LiteSpeed load balancer can run in a chroot environment also known as a chroot jail with an automatic initial chroot environment setup. In a chrooted environment, the load balancer and its children processes cannot access the file system outside of the chroot jail. This protects the system from attacks caused by malicious code.

3D INTEGRATED CIRCUIT

GLOBAL Semiconductor Alliance says it will increase awareness and visibility worldwide for its 3D integrated circuit initiative.

The GSA has retained semiconductor industry veteran, Herb Reiter to lead the 3D IC initiative. It has also formed relationships with IMEC, ITRI, SEMI, SEMATECH and Si2 to help direct and participate in this effort.

The GSA says it has presented papers and gained awareness for 3D IC at multiple global events, such as DATE 2010 in Dresden, DAC, SemiCon West and the GSA Emerging Opportunities Expo and Conference.

According to the Alliance, the 3D IC initiative will be a major feature of its second annual Memory Conference on 31 March 2011 in San Jose. The theme for the 2011 conference will be “Memory and Logic Integration and the Benefits of 3D IC Technology”.

The Alliance claims 3D IC is a way forward in the face of the challenges of rapidly increasing power dissipation of ICs and systems.

The wireless industry is also pushing for 3D IC stacks to meet the power and space constraints in Mobile Internet Devices, and the technology is expected to help meet next generation bandwidth and performance requirements.

History of the Integrated Circuit aka Microchip

D you know Integrated Circuit . What we didn't realize then was that the integrated circuit would reduce the cost of electronic functions by a factor of a million to one, nothing had ever done that for anything before" - Jack Kilby

The Integrated Circuit

It seems that the integrated circuit was destined to be invented. Two separate inventors, unaware of each other's activities, invented almost identical integrated circuits or ICs at nearly the same time.Patents for the Integrated Circuit

In 1959 both parties applied for patents. Jack Kilby and Texas Instruments received U.S. patent #3,138,743 for miniaturized electronic circuits. Robert Noyce and the Fairchild Semiconductor Corporation received U.S. patent #2,981,877 for a silicon based integrated circuit. The two companies wisely decided to cross license their technologies after several years of legal battles, creating a global market now worth about $1 trillion a year.

Commercial Release

In 1961 the first commercially available integrated circuits came from the Fairchild Semiconductor Corporation. All computers then started to be made using chips instead of the individual transistors and their accompanying parts. Texas Instruments first used the chips in Air Force computers and the Minuteman Missile in 1962. They later used the chips to produce the first electronic portable calculators. The original IC had only one transistor, three resistors and one capacitor and was the size of an adult's pinkie finger. Today an IC smaller than a penny can hold 125 million transistors.

Jack Kilby holds patents on over sixty inventions and is also well known as the inventor of the portable calculator (1967). In 1970 he was awarded the National Medal of Science. Robert Noyce, with sixteen patents to his name, founded Intel, the company responsible for the invention of the microprocessor, in 1968. But for both men the invention of the integrated circuit stands historically as one of the most important innovations of mankind. Almost all modern products use chip technology.

7402 Quad 2-input NOR gate

function = Quad 2-input NOR gate
package = DIP-14

Family: Std, ALS, AS, LS, S, ACT, AC, HCT,


HC, C, H, L.

Other package types: SMD, Flat, 20Chip.
Equivalent types: CN88DP, D102C, FJH221,
FLH191, HD2511, DL002D (LS).
7402 Quad 2-input NOR gate

Truth table:
----------------
|In1 |In2 |Out |
|--------------|
|  H  |  H  |  L  |
|  H  |  L   |  L  |
|   L  |  H  |  L  |
|   L  |  L  |  H  |
----------------

PINOUT

01: Output Gate 1
02: Input 1 Gate 1
03: Input 2 Gate 1
04: Output Gate 2
05: Input 1 Gate 2
06: Input 2 Gate 2
07: GND
08: Input 1 Gate 3
09: Input 2 Gate 3
10: Output Gate 3
11: Input 1 Gate 4
12: Input 2 Gate 4
13: Output Gate 4
14: Vcc

7401 Quad 2-input NAND gate

Add caption

function = Quad 2-input NAND gate
package = DIP-14

Family: Std, ALS, AS, LS, S, HC, F, H, L.


Equivalent types: 1LB558, CN86DP, D101C,

FJH231, FLH201, HD2509, K155LA8, K555LA8 (LS)
Open collector outputs.
Other package types: SMD, Flat, 20Chip.

Truth table:
----------------
|In1 |In2 |Out |
|----------- --|
|  H | H |  L  |
|  H |  L |  H |
|  L |  H |  H |
|  L |   L |  H |
----------------

PINOUT

01: Output Gate 1
02: Input 1 Gate 1
03: Input 2 Gate 1
04: Output Gate 2
05: Input 1 Gate 2
06: Input 2 Gate 2
07: GND
08: Input 1 Gate 3
09: Input 2 Gate 3
10: Output Gate 3
11: Input 1 Gate 4
12: Input 2 Gate 4
13: Output Gate 4
14: Vcc

7400 Quad 2-input NAND gate

function = Quad 2-input NAND gate
package = dip-14

Family: Std, AC, ACT, ALS, AS, LS, S, HCT,


HC, C, F, H, L.
Equivalent types: 1LB553, CDB400E, CN78DP,
D100C, FJH131, FLH101, HD2503, K155LA3,
K555LA3 (LS), DL000D (LS), D200D (H).
Other package types: SMD, Flat, 20Chip.

Truth table:
----------------
|In1 |In2 |Out |
|--------------|
| H | H | L |
| H | L | H |
| L | H | H |
| L | L | H |
----------------

pinout

01: Input 1 Gate 1
02: Input 2 Gate 1
03: Output Gate 1
04: Input 1 Gate 2
05: Input 2 Gate 2
06: Output Gate 2
07: GND
08: Output Gate 3
09: Input 1 Gate 3
10: Input 2 Gate 3
11: Output Gate 4
12: Input 1 Gate 4
13: Input 2 Gate 4
14: Vcc